1. Field of the Invention
The present invention generally relates to a voltage generating circuit which can be used in a reference voltage generating circuit, a temperature compensating circuit of a voltage comparator, a current source including a combination of a temperature sensor and a resistor having a linear temperature characteristic, and so forth. In particular, the present invention relates to a voltage generating circuit employing field effect transistors (which will be described in examples in which MOS-type field effect transistors are employed) generating a voltage proportion to the absolute temperature (PTAT: Proportional-To-Absolute-Temperature).
Further, the present invention relates to a reference voltage source circuit used in an analog circuit or the like, in particular, a reference voltage source circuit employing field effect transistors (which will be described in examples in which MOS-type field effect transistors are employed) which operates stably even at a temperature not lower than 80° C., generates a voltage proportional to the absolute temperature (PTAT) and thus has a desired temperature characteristic.
2. Description of the Related Art
A PTAT circuit is known as a voltage generating circuit employing bipolar transistors. A PTAT circuit which achieves this art by utilizing a weak inversion range of a MOS (or CMOS) transistor has been also proposed. Further, as a reference voltage source, a reference voltage source such that a voltage source having a positive temperature coefficient is produced by causing a field effect transistor to operate in a weak inversion range, and, using it, a reference voltage source having a small variation in characteristic with respect to temperature is achieved is also known. These arts will now be described.
For example, E. Vittoz and J. Fellrath, “CMOS Analog Integrated Circuits Based on Weak Inversion Operation”, Vol. SC-12, No. 3, pages 224-231, June, 1997 (reference B) discloses a PTAT (Proportional-To-Absolute-Temperature) employing CMOS transistors. Thereby, a drain current ID in a weak inversion range is given by the following equation:ID=SIDOexp(VG/nUT){exp(−VS/UT)−exp(−VD/UT)}There, VG, VS and VD denote a voltage between a substrate and a gate, a voltage between the substrate and a source, and a voltage between the substrate and a drain, respectively; S denotes a ratio (Weff/Leff) of effective channel width W and channel length L; IDO denotes a characteristic current determined by process technology; n denotes a slope factor (rising characteristic in a weak inversion range); and UT denotes kT/q. There, k denotes the Boltzmann's constant; T denotes the absolute temperature; and q denotes the charge of carrier (electron).
Further, Tsividis and Ulmer, “A CMOS Voltage Reference”, IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 6, pages 774-778, December, 1978 (reference A) discloses, as shown in FIG. 1 of the present application, currents I1 and I2 are caused to flow through source-connected n-type-channel transistors T1 and T2, respectively, and, as a difference between gate voltages (V1−V2), a VPTAT is obtained as follows (see FIG. 4 of the reference A):VPTAT=V1−V2=nUTln{(S2I1)/(S1I2)}
Further, in FIG. 1, where the voltage drop between base and emitter of the bipolar transistor is referred to as Vbe, and the output is referred to as Vo,
 Vbe+V1=V2+Vo
Accordingly, the output Vo is obtained as follows:Vo=Vbe+(V1−V2)=Vbe+VPTATThe base-emitter voltage Vbe of the bipolar transistor at the first term has a negative temperature coefficient with respect to the absolute temperature. Further, VPTAT at the second term has a positive temperature coefficient with respect to the absolute temperature. Accordingly, the output Vo obtained from addition thereof has a flat temperature characteristic.
Further, E. Vittoz and O. Neyroud, “A low-voltage CMOS bandgap reference”, IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 3, pages 573-577, June, 1979 (reference C) discloses, as shown in FIG. 2 of the present application, the same current I is caused to flow through gate-connected n-type-channel MOS transistors Ta and Tb, and, as a difference in source voltages therebetween, Vo is obtained as follows (see FIG. 7 of the reference C):Vo=VPTAT=UTln(1+Sb/Sa)
The VPTAT output in each of the above-mentioned references A and C is also proportional to UT=kT/q.
Further, Oguey et al., “MOS Voltage Reference Based on Polysilicon Gate Work Function Difference”, IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 3, June, 1980 (reference D) discloses, as shown in FIG. 3 of the present application, a transistor T1 having a p+ polysilicon gate and a transistor T2 having n+ polysilicon gate are used as input transistors of a differential amplifier, each of these transistors is biased into a weak inversion range, a difference between the gate voltages VR=VG1−VG2=ΔVG+UTln(ID1S2/ID2S1), the bandgap of the silicon ΔVG and VPTAT: UTln(ID1S2/ID2S1) are obtained.
Further, becauseΔVG=ΔVG0−αmTit is assumed that αmT=UTln(ID1S2/ID2S1), and a voltage VR which does not depend on the temperature is obtained as follows (see FIG. 9 of the reference D):VR=ΔVGO=1.20(V)
Thus, in the related arts, VPTAT is achieved by utilizing a weak inversion range of a MOS transistor instead of a bipolar transistor. However, when the weak inversion range is utilized, the following problems may occur:
a) Problem that, in order to cause a gate of a MOS transistor to enter a weak inversion range, a minute-current biasing circuit for weak inversion is needed:
According to the above-mentioned reference B (see the equation (12) of the reference), a drain current should satisfy the following condition in order to keep the MOS transistor in the weak inversion range:I≦{(n−1)/e2}SμCoxUT2There, n denotes a slope factor, S denotes the ratio (Weff/Leff) of effective channel width W and channel length L, μ denotes the mobility of carriers in channel, and Cox denotes the capacitance of the oxide film per unit area.
Specifically, as disclosed in U.S. Pat. No. 4,327,320, April, 1982, “Reference Voltage Source”, Oguey (reference E), when n=1.7, S=1, μ=750 (cm2/Vs), Cox=45 (nF/cm2), and UT=26 (mV), the drain current at the room temperature should be a minute one not larger than 2 nA.
b) Problem due to Influence of Parasitic Diode:
However, when operation is made in a condition of a minute drain current not larger than 2 nA as mentioned above, it is easy to be affected by a leakage current due to a parasitic diode between the drain and substrate. For example, in the above-mentioned reference D, page 268, it is disclosed that, at a temperature not lower than 80° C., a problematic shift due to a leakage current occurs.
c) Problem that a current biasing circuit is needed for correcting a temperature characteristic of conductivity:
As disclosed U.S. Pat. No. 4,417,263, Y. Matsuura, November, 1983 (corresponding to Japanese Patent Publication No. 4-65546, reference G), by using a difference in threshold voltage between a depletion-type transistor and an enhancement-type transistor produced to have different substrate concentrations and/or channel dopings, and making conductivity thereof to be approximately equal, a reference voltage is obtained. However, a pair of MOS transistors, produced to have different substrate concentrations and/or channel dopings, have different conductivities and/or different temperature characteristics thereof. Accordingly, as disclosed by R. A. Blauschild et al., “A New NMOS Temperature-Stable Voltage Reference”, Vol. SC-13, No. 6, pages-767-773, December, 1978 (reference F), a current biasing circuit for correcting the temperature characteristic of conductivity is needed.